1. Field of the Invention
The present invention relates generally to a process for preparing an electronics structure using a sacrificial multilayer hardmask scheme, to a process of preparing an electronic device incorporating the electronics structure preparation process, and to electronics structures useful in both processes.
2. Description of Related Art
The fabrication of Very-Large Scale Integrated (VLSI) or Ultra-Large Scale Integrated circuit (ULSI) requires metallic wiring that connects individual devices in a semiconductor chip, to one another. One method of creating this wiring network on such small scale is the dual damascene (DD) process schematically shown in FIG. 1. In the standard DD process, an interlayer dielectric (ILD), shown as two layers PA1-110, PA1-120 is coated on the substrate PA1-100, FIG. 1a. The via level dielectric PA1-110 and the line level dielectric PA1-120 are shown separately for clarity of the process flow description. In general, these two layers can be made of the same or different insulating films and in the former case applied as a single monolithic layer. A hard mask layer PA1-130 is optionally employed to facilitate etch selectivity and to serve as a polish stop as will be seen later. The wiring interconnect network consists of two types of features: line features that traverse a distance across the chip, and the via features which connect lines in different levels together. Historically, both layers are made from an inorganic glass like silicon dioxide (SiO.sub.2) or a fluorinated silica film deposited by plasma enhanced chemical vapor deposition (PECVD).
In the dual damascene process, the position of the lines PA1-150 and the vias PA1-170 are defined lithographically in photoresist layers, PA1-140, depicted in FIGS. 1b and 1d, and transferred into the hard mask and ILD layers using reactive ion etching processes. The process sequence shown in FIG. 1 is called a line-first approach because the trench PA1-160 which will house the line feature is etched first, see FIG. 1c. After the trench formation, lithography is used to define a via pattern PA1-170 in the photoresist layer PA1-140 which is transferred into the dielectric material to generate a via opening PA1-180, FIG. 1d. The dual damascene trench and via structure PA1-190 is shown in FIG. 1e after the photoresist has been stripped. This structure PA1-190 is coated with a conducting liner material or material stack PA1-200 that serves to protect the conductor metal lines and vias and serve as an adhesion layer between the conductor and the ILD. PA1-200 also serves to facilitate electroplating. This recess is then filled with a conducting fill material PA1-210 over the surface of the patterned substrate. The fill is most commonly accomplished by electroplating of copper although other methods such as chemical vapor deposition (CVD) and other materials such as Al or Au can also be used. The fill and liner materials are then chemically-mechanically polished (CMP) to be coplanar with the surface of the hard mask and the structure at this stage is shown in FIG. 1f. A capping material PA1-220 is deposited over the metal or as a blanket film, as is depicted in FIG. 1g to passivate the exposed metal surface and to serve as a diffusion barrier between the metal and any additional ILD layers to be deposited over them. Silicon nitride, silicon carbide, and silicon carbonitride films deposited by PECVD are typically used as the capping material PA1-220. This process sequence is repeated for each level of the interconnects on the device. Since two interconnect features are defined to form a conductor in-lay within an insulator by a single polish step, this process is designated a dual damascene process.
As with any circuit, semiconductor chips are prone to signal propagation delays which depend on the product of the line resistance, R, and the interconnect capacitance, C. In order to improve the performance of semiconductor chips, manufacturers have reduced the resistivity of the metal used in fabrication by replacing aluminum wiring by copper. By moving to lower dielectric constant (k) materials, manufacturers have also begun to reduce the capacitance, C, in the circuit. The common terminology used to describe the dielectric films is to classify them as standard k (4.5<k<10), low k (k<3.0), ultra low k (2.0<k<2.5) and extreme low k (k<2.0). Ultra low k and extreme low k dielectrics generally tend to be porous with intentionally engineered voids in their structure. Since the lowest dielectric constant possible is defined by air or vacuum (k.sub.vac=1), many have developed means to produce voids in the dielectric. When the void volume extends and occupies substantial contiguous regions of the gaps between the lines one achieves an interconnect structure wherein the lines are nominally separated by air or vacuum as the ILD material. In the following descriptions, the term “air bridge” is used to describe such an interconnect structure to distinguish it from structures wherein the ILD is porous with void volume dispersed randomly within a nominally contiguous solid dielectric. Examples of air bridges can be found in V. Arnal et al., Microelectronic Engineering, 2003, Volume 70, pp. 274-279, and P. A. Kohl et al., Electrochemical and Solid-State Letters, 1998, Volume 1, Number 1, pp. 49-50.
The use of bottom-up approaches to semiconductor fabrication has grown in interest within the scientific community (J. Alex Liddle et al., J Vac. Science Technology, November/December 2004, Volume 22, Number 6, pp. 3409-3414; T. P. Russell et al., Science, Dec. 15, 2000, Volume 290, pp. 2126-2129; C. T. Black et al., Applied Physics Letters, Jul. 16, 2001, Volume 79, Number 3, pp. 409-411; and K. W. Guarini et al., J Vac. Science Technology, November/December 2002, Volume 20, Number 6, pp. 2788-2792). One such approach utilizes block copolymers for generating sub-optical ground rule patterns. In particular, one illustrative use is forming a “honeycomb” structure within a poly(methyl methacrylate-b-styrene) block copolymer. In the case of a cylindrical phase diblock having a minor component of PMMA, the PMMA block can phase separate to form vertically oriented cylinders within the matrix of the polystyrene block upon thermal anneal (T. P. Russell et al., Science, Dec. 15, 2000, Volume 290, pp. 2126-2129).
This prior art process is shown in FIG. 2. A substrate PA2-100 is coated (optionally) with a random copolymer PA2-110. This copolymer is affixed to the surface and excess material is washed away. A block copolymer PA2-120 is coated on the top surface of the random-substrate stack as shown in FIG. 2a. The block copolymer PA2-120 is annealed with heat and/or actinic irradiation PA2-130 allowing for phase separation of the immiscible polymer blocks PA2-121 and PA2-122. The annealed film is then developed to reveal a pattern PA2-123 that is commensurate with the positioning of one of the blocks in the copolymer. For simplicity, the block is shown as complete removed although this is not required. Other means of nanocolumnar formation in diblock copolymer films have been shown such as ‘solvent-mediated formation’ by T. Russell (T. P. Russell et al., Advanced Materials, Feb. 3, 2004, Volume 16, Number 3, pp. 226-231).
Since block copolymers have a natural length scale associated with their molecular weight and composition, the morphology of a phase-separated block copolymer can be tuned to generate cylinders of a specific width and on a specific pitch. Literature shows the use of UV exposure to cause the PMMA to decompose into smaller molecules (T. P. Russell et al., Science, Dec. 15, 2000, Volume 290, pp. 2126-2129) and, further, developed using glacial acetic acid to remove the small molecules. Others simply develop the acetic acid to reveal the HCP pattern (K. W. Guarini et al., J Vac. Science Technology, November/December 2002, Volume 20, Number 6, pp. 2788-2792 and C. T. Black et al., Applied Physics Letters, Jul. 16, 2001, Volume 79, Number 3, pp. 409-411).
In FIG. 3, one prior art approach to air bridge construction is shown. It incorporates the prior art build shown in FIG. 1 and patterning techniques such as that shown in FIG. 2. In this process, a low-k structure is constructed after metal deposition steps to form the interconnects. For the purpose of reference, these types of processes are designated in the present application as metal-then-air bridge (MAB) approaches consistent with the process sequence used. Most processes that follow this approach begin with the standard DD fabrication sequence. Thus the process flow is consistent with FIG. 1. After the metallization step and either before or after the dielectric capped deposition, a nanometer scale pattern is transferred into the underlying interconnect structure and capped with a barrier material PA3-140. Thus, for example, the structure shown in FIG. 3 is identical to the DD structure shown in FIG. If except the dielectric stack has nanocolumnar voids or pillars PA3-150 in the dielectric stack PA3-120 on the substrate PA3-100. Additionally it can be seen that the dielectric PA3-110 under the metallic lines PA3-130 is solid. Additional levels can then be fabricated in the same manner above the air bridge level.
One disadvantage to this process is the exposure of the metallic line to harsh reactive ion etch processes generally required for patterning of the dielectric. It is therefore clear that an alternate approach that will circumvent the above detailed limitation of this MAB approach is needed in order to fabricate reliable multilevel air bridge structures.